Scaling 800V+ Infrastructure in the AI Data Center Supply Chain

The migration from 400V to 800V+ DC bus architecture inside AI data centers is the central engineering theme of 2026. The efficiency argument is unambiguous: higher bus voltage reduces I²R losses, enables single-stage DC-DC conversion (eliminating intermediary conversion steps), and compresses the physical footprint of power supply systems — directly addressing the rack density problem driving AI infrastructure design.

Wolfspeed's TOLT (TO-Leaded, Top-Side Cooled) portfolio, launched January 29, 2026, is purpose-built for this migration. Built on Gen 4 MOSFET technology, TOLT enables maximum power density in rack power supplies by releasing heat from the top side of the package — allowing more efficient thermal path management in high-density configurations. The 650V TOLT devices are now available in multiple RDS(on) options; a third top-side-cooled portfolio family is expected H2 2026.

Nvidia has announced plans to adopt an 800VDC power conversion system co-developed with Vertiv for its next-generation Vera Rubin AI accelerator systems. This is not a product roadmap — it is an architectural standard becoming embedded in hyperscaler procurement requirements. Once a major chip platform mandates 800V, the entire downstream supply chain (power supplies, bus bars, connectors, protection circuits) must conform.

Thermal management is the area with the clearest near-term revenue trajectory and the fewest technical unknowns. The transition from air-cooled architectures to direct-to-chip and immersion liquid cooling is no longer optional at AI-scale rack densities — it is a physical constraint being imposed by GPU thermal envelopes that standard CRAC and in-row cooling cannot accommodate.

Vertiv's financial performance is the empirical proof: 252% year-over-year organic order growth in Q4 2025, a $15 billion backlog (up 109% year-over-year), and 2026 guidance calling for 27–29% organic growth and net sales of $13.25–$13.75 billion. The company's Q1 FY26 result delivered 30% revenue growth to $2.6 billion with 83% adjusted EPS growth — at an adjusted operating margin of 20.8%. This is not a company catching the AI wave; it is the wave's infrastructure floor.

Vertiv's portfolio covers the full cooling transition spectrum: Vertiv 360AI, SmartRun prefabricated overhead infrastructure (integrating secondary fluid networks for direct-to-chip cooling, deployable up to 85% faster than stick-build), MegaMod HDX (prefabricated power and liquid cooling), and Next Predict (AI-powered predictive maintenance). The Nvidia partnership for 800VDC systems locks Vertiv into the dominant AI chip platform's deployment lifecycle.

The emerging competitive dynamic: as rack power densities continue to increase toward 120–200kW and beyond, direct-to-chip cooling is becoming the only viable thermal management approach for high-end AI accelerators. This creates a structural demand floor for liquid cooling infrastructure that is not cyclical — it is architectural.

Advanced packaging has transitioned from a supporting process to the primary enabler of AI chip performance. The limits of transistor scaling have pushed the industry toward chiplets, 2.5D interposers (CoWoS), 3D stacking, and heterogeneous integration — each requiring specialized packaging equipment and materials that did not exist in volume three years ago.

Applied Materials (AMAT) occupies the highest-value position in this transition. The company holds the #1 process equipment position for leading-edge foundry logic, DRAM, and high-bandwidth memory packaging. CEO Gary Dickerson guided the semiconductor equipment business to grow over 20% in calendar 2026 — a figure that may prove conservative given the parallel ramps at TSMC, Samsung, and SK Hynix. AMAT's Q1 FY2026 delivered $7.01 billion revenue with 49% gross margins. The company has doubled its system manufacturing capability in recent years and now has demand visibility extending one to two years, rather than the typical single quarter.

The packaging bottleneck is currently concentrated at TSMC's CoWoS (Chip on Wafer on Substrate) capacity. Every AI GPU requiring 2.5D integration — Nvidia H100, H200, B100, and the upcoming Vera Rubin — runs through CoWoS. This creates a structural constraint that is not resolved by capital alone; it requires 18–24 months to bring new CoWoS capacity online. TSMC is breaking ground on advanced packaging facilities in Arizona to reduce Taiwan-centric concentration risk.

Lam Research projects its advanced packaging business to grow over 40% in fiscal 2026. Applied Materials' acquisition of a 9% stake in BE Semiconductor (BESI) in 2025 signals a strategic interest in hybrid bonding — the next-generation die attachment technology essential for 3D stacked AI chips.

Inside AI data centers operating at 800V+ and extreme power densities, electromagnetic interference (EMI) from switching transients creates a fundamental challenge for copper-based interconnects. The combination of high-frequency SiC switching, dense rack configurations, and tight rack-to-rack distances is accelerating the transition from copper to optical interconnects — not as a premium option, but as an engineering necessity at scale.

Marvell Technology has established itself as the critical infrastructure layer for this transition. The company's 1.6 Tb/s PAM4 optical DSP (Ara T) is the first 8x200G transmit-retimed optics (TRO) PAM4 DSP — a generational jump in optical interconnect performance that is defining the emerging standard for AI scale-out networking. Marvell's Photonic Fabric platform enables multi-rack optical scale-up meeting the reach, bandwidth, latency, and energy demands of next-generation AI clusters.

The financial trajectory validates the technology thesis. Marvell's data center revenue grew 46% year-over-year in fiscal 2026 and crossed a $6 billion run rate. Custom ASIC revenue sits at a $1.5 billion annual run rate and is projected to scale to $9–$11 billion of AI ASIC revenue in 2026 as design wins convert to production. The company guides fiscal 2027 revenue to nearly $11 billion (>30% growth) and fiscal 2028 to $15 billion. Nvidia's $2 billion equity stake in Marvell in March 2026 — the NVLink Fusion partnership — is the external validation that silicon photonics is the long-term interconnect winner.

Marvell's acquisition of Celestial AI ($3.25 billion, December 2025) adds co-packaged optics (CPO) technology — placing optical components inside the chip package itself to eliminate the copper bottleneck entirely. CPO revenue is projected at a $500M annualized run rate by Q4 FY2028.

The grid-to-chip power chain is the least-discussed but potentially largest long-term opportunity for SiC technology in the AI data center buildout. Conventional iron-core transformers at medium-voltage grid interconnection points are a critical bottleneck: they are heavy, slow to manufacture (12–18 month lead times for large units), and incapable of the dynamic power conversion capabilities that AI data centers — with their rapidly variable load profiles — require.

Solid-State Transformers (SSTs) using SiC power electronics solve this directly. Wolfspeed's 10kV SiC MOSFET — the industry's first commercially available device at this voltage — is specifically designed for SST applications. Key performance claims: 99% conversion efficiency, 30% lower system cost versus silicon IGBT alternatives, and 300% higher power density. At 10kV, a single SiC-based SST can interconnect directly to medium-voltage grids (4kV–35kV) without the intermediate step-down transformers that add cost, weight, and conversion loss.

The commercial ecosystem for SiC SSTs is forming rapidly: Infineon/DG Matrix (Interport platform with 98.5% efficiency), SolarEdge/Infineon (2–5MW modular SST building blocks for hyperscale), Amperesand (30MW deployments for hyperscale data centers planned 2026), and Navitas/EPFL (250kW SST demonstrator at APEC 2026 converting 3.3kVAC to 800VDC directly). Each represents a different commercialization path for the same underlying SiC device technology.

Every technology layer in this report — SiC wafers, advanced packaging, optical interconnects, solid-state transformers — requires inspection and metrology capability that did not exist at production scale five years ago. The quality control challenge for wide-bandgap semiconductors is qualitatively different from silicon: SiC crystal defect density, micropipe density, basal plane dislocation concentration, and epitaxial layer uniformity must all be characterized at a level of precision that demands specialized inspection equipment.

Camtek (CAMT) occupies the most relevant position in the AI infrastructure quality control stack. The company's Eagle inspection systems are deployed in advanced packaging production lines, and its HERCULES inspection platform addresses the heterogeneous integration challenges of 2.5D/3D chip stacking. Camtek's revenue grew approximately 36% year-over-year in 2025, driven by advanced packaging demand from AI chip production.

KLA Corporation (KLAC) is the broader-market leader in process control and yield management, with metrology tools deployed across the full semiconductor manufacturing stack. AMAT's own metrology capabilities — integrated with its deposition and etch tooling — provide a closed-loop quality system for leading-edge nodes. As SiC power chips move to 300mm and advanced packaging becomes more complex (CoWoS → 3D stacking → CPO), the inspection requirement per wafer increases non-linearly, creating a natural volume multiplier on inspection equipment demand.

The optical inspection challenge specific to SiC and power electronics packaging is underappreciated: unlike standard silicon, SiC substrates have lower thermal conductivity and different thermal expansion coefficients — making traditional silicon-calibrated inspection tools insufficient without adaptation.